1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which forms a pattern by performing pattern transformation steps multiple times, and relates to a computer readable medium for storing a pattern size setting program capable of setting optimum size for each pattern formed in each pattern transformation step.
2. Description of the Related Art
In the development of a semiconductor integrated circuit, downsizing of a pattern has been progressing year by year. Such progress of pattern downsizing has depended on a photolithography technique, and the trend of pattern downsizing is likely to continue for some years. The pattern size in photolithography (i.e. half pitch (HP)) can be represented by the following Rayleigh formula based on a wavelength (λ) of an exposure device used in achieving that pattern size and the number of lens apertures (NA).HP=k1×λ/NA 
If a pattern pitch is to be determined by the needs in the market, a factor k1 in this formula will show a degree of difficulty in achieving such pattern pitch. The factor k1 will be a process constant which is determined mainly based on resist performance, device controllability, a pattern of a reticle, and process controllability. Accordingly, in the above formula, it can be understood that lithography is difficult when the factor k1 is small.
Due to the progress of downsizing in a semiconductor device in recent years, a pattern size with a factor k1 that is less than 0.25, which is a theoretical limit in lithography, has been required. In a level with such pattern size, a method of forming a pattern pitch which is smaller than a minimum pattern pitch capable of being formed by lithography is required. Conventionally, as one of such methods, a downsizing processing method using a sidewall process has been proposed (e.g. U.S. Pat. No. 6,383,952, U.S. Pat. No. 6,475,891).
Now, one example of the conventional downsizing processing method using the sidewall process will be described. In this example, first, a sacrifice film is stacked on a process target layer, which may be a substrate, etc., after which the sacrifice film is patterned through a lithography step and a processing step. Then, a sidewall material is deposited on the sacrifice film to a desired thickness, after which the sidewall material formed in a part of the sacrifice film pattern other than a sidewall portion is removed, and then the sacrifice film is removed in a way leaving the sidewall portion of the sacrifice film pattern. Then, by performing an etching process using this sidewall portion as a mask, the process target layer is formed into a desired pattern.
However, the above-described conventional sidewall process requires processing of the sacrifice film; deposition of the sidewall material; removal of a part of the sidewall material; removal of the sacrifice film; etching process using the sidewall portion as the mask; and the like, which are more complicated process steps than in the conventional process where the process target layer is patterned using a resist pattern as a mask. Therefore, variation in size of each pattern as formed in each process step accumulates to cause a problem in that the size of the pattern eventually formed in the process target layer will vary greatly depending on the position of the pattern within the element formation surface. For example, in a case when the sidewall process is adopted in wiring pattern formation and when a size of a pattern is varied considerably, inter-wiring capacitance will become large, and as a result, a circuit operation speed will decrease. Moreover, in a case when the sidewall process is adopted in gate pattern formation, possible variations in a line size may cause short-channel of a transistor whereby a malfunction of the transistor can be caused, or long-channel of a transistor whereby a circuit speed can be decreased as a current value becomes insufficient.